Experience Sharing of Decoupling Capacitor Placement in PCB Layout

March 22, 2021

With the development of science and technology era, the requirement of chip is more and more stringent, and the requirement of PCB layout is also more stringent. The experience of decoupling capacitor placement of SEPRAYS milling cutter PCB splitter in PCB layout arrangement is mainly discussed from two aspects: PCB capacitor and pad design.


For capacitor installation, the first thing to mention is the installation distance. The capacitor with the smallest capacitance has the highest resonant frequency and the smallest decoupling radius, so it is placed nearest to the chip. If the volume is slightly larger, the distance is slightly longer, and the maximum volume is placed in the outermost layer. However, all capacitors that decouple the chip are as close to the chip as possible.


The following figure is an example of placement. The capacitance level in this case follows a 10-fold hierarchy.


It is also important to note that when placed, it is best to distribute evenly around the chip, for each volume level. Usually, when designing a chip, the arrangement of power supply and ground pins is taken into account. Generally, the chip is evenly distributed on the four sides of the chip. Therefore, voltage disturbance exists all around the chip, and decoupling must be uniform in the whole chip area. If the 680pF capacitors in the figure above are placed on the top of the chip, the voltage disturbance at the bottom of the chip can not be decoupled well because of the problem of decoupling radius.




Capacitance Installation


When installing capacitance, pull out a small section of lead wire from the pad, then connect through the hole and the power plane, and the ground end is the same. In this way, the current loop flowing through the capacitor is: the power plane - "through hole -" lead wire - "pad -"capacitance - "lead wire -"through hole - "horizon. Figure 2 shows the current reflux path intuitively.


The first method is to draw a long lead wire from the pad and then connect the holes. This will introduce a large parasitic inductance. It must be avoided. This is the worst way to install it.


The second method has much smaller pavement area and less parasitic inductance than the first method, and it is acceptable to drill holes near the two ends of the pad.


The third method is to drill holes on the side of the pad, which further reduces the area of the circuit. The parasitic inductance is smaller than the second one, and it is a better method.


The fourth method is to drill holes on both sides of the pad. Compared with the third method, each end of the capacitor is connected to the power supply plane and the ground plane in parallel through the holes, which is smaller than the third parasitic inductance. As long as space permits, try to use this method.


The last method is to drill holes directly on the pad, and the parasitic inductance is the smallest. However, welding may cause problems. Whether it is used depends on the processing ability and method. The third and fourth methods are recommended.


It should be emphasized that in order to save space, some engineers sometimes let multiple capacitors use common through holes, which should not be done under any circumstances. It is best to find ways to optimize the design of capacitor combination and reduce the number of capacitors.


Because the wider the printed line, the smaller the inductance, the wider the lead-out line from the pad to the through hole, and if possible, the same width as the pad. This allows you to use a 20MIL wide lead wire even for 0402 packaged capacitors. Lead-out line and through hole installation as shown in the figure above, pay attention to the various sizes in the figure.


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